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InnoPhase IoT

Principal Engineer, PHY/MAC Design (P)

San Jose, USAPosted 2 days ago

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Job type
Full-time
Work mode
Not listed
Level
Principal
Department
Engineering
Experience
10+ years experience
Posted
Oct 1, 2026

About the role

About InnoPhase IoT

If you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you’ll find your playground at Innophase IoT.

We are looking for people seeking AWESOMENESS! If you’re good at what you do, you can work anywhere. If you’re the best at what you do, come work at Innophase IoT!

Job duties

  • Develop end-to-end simulation frameworks for sophisticated wireless systems.
  • Work spanning the full signal chain from propagation channel modeling and RF/antenna behavior to PHY & MAC protocols and signal processing algorithms.
  • Develop and refine Digital Signal Processing engines for wireless communication systems.
  • Develop micro-architecture, and System Verilog RTL to meet size, timing, and power target.
  • Analyze, and identify bottlenecks in design and provide feedback on micro-architecture, and optimizations.
  • Develop, and refine design, verification and analysis tools and flows.
  • Work closely with Verification, and Validation teams on test-plans, coverage-analysis
  • Work closely with Physical Design teams to provide guidance on Floor planning, specification of constraints, and timing closure.

Education and Experience

Masters degree in Electrical Engineering, or a related field, plus ten (10) years of relevant experience. Must also have:

  • Experience in ASIC development and/or FPGA prototyping
  • Experience in RTL design using Verilog, SystemVerilog
  • Understanding of Digital Signal Processing theory, and mapping to design
  • Experience in WiFi Physical Layer, or other Physical layer such as Cellular
  • Experience with VCS, Verdi, Spyglass, or equivalent tools
  • Experience in synthesis, timing closure for FPGA and ASICs
  • Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.

Up to 15% domestic travel.