Sr. Staff Power Performance Architect

Role Overview

d-Matrix is looking for a Senior Staff Power Performance Architect to own pre-silicon power estimation across our next-generation AI accelerators. In this role, you will drive both RTL-level and physical-design-level power estimation, and build an architectural power estimation tool that models power from system configuration and die-level metrics for AI workloads. You will partner closely with front-end architects, DV engineers, and backend design teams to identify power activity windows, define performance monitoring requirements, and translate that analysis into hardware capability improvements and die-level design changes. This role also contributes directly to micro-architecture and RTL design, verification, and silicon bring-up, making it central to how d-Matrix balances performance and power efficiency at the silicon level.

What You Will Do

• Own pre-silicon power estimation for design blocks, spanning both RTL-level and physical-design-level estimation.
• Partner with front-end and DV engineers to identify power activity windows, and work with the RTL team to implement estimation feedback and optimize power.
• Build an architectural power estimation tool for AI workloads that computes power from system configuration and die-level metrics, including workload profiling based on memory size, bandwidth, and gate counts of compute/memory blocks.
• Collaborate with frontend architects and backend design to define performance monitor availability, system requirements, and usage, then drive that analysis into hardware capability improvements and die-level design modifications.
• Lead micro-architecture and RTL design, synthesis, and logic/physical power-performance verification using leading-edge CAD tools and semiconductor process technologies.
• Design and implement performance-enabling and power-saving/monitoring functions that support efficient design, test, and debug, and participate in silicon bring-up and validation.

What You Will Bring

• 8+ years of relevant experience in IC power/performance architecture, RTL, or physical design, with a Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Solid understanding of power, performance, micro-architecture, RTL, and physical design in the context of digital system and IC design, including the full IC design flow (Arch → uarch → RTL → Schematic → Layout → Verification → Fabrication → HVM).
• Familiarity with at least one EDA tool for power estimation.
• Ability to move fluidly between RTL, physical design, and automation, including building script utilities to improve design execution productivity across the design team.
• Programming proficiency in TCL and Python, with experience using libraries, APIs, data parsing, and algorithmic thinking.
• Self-motivated with a fast, iterative approach to design work, sound engineering judgment, and a bias toward action.

Preferred Qualifications

• Exposure to power estimation and performance metrics such as TDP, PMAX, EDP, Peak, and Average.
• Familiarity with power/frequency scaling techniques (DFS, DVFS, AFS, AVFS).
• Familiarity with power delivery network (PDN) analysis, including resonance, impedance (Z(f)), and voltage droop analysis.