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Astera Labs

Tech Lead, Digital Design Engineer

San Jose, USAPosted 5 days ago

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Job type
Not listed
Work mode
Not listed
Level
Lead
Department
Engineering
Experience
3+ years experience
Posted
Sep 28, 2026

About the role

Job Description

We are looking for Senior Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.

Basic Qualifications:

  • Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
  • +3 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
  • Authorized to work in the US and start immediately.

Required Experience:

  • Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
  • Proven front end design skill – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
  • Block level ownership from architecture to GDS.
  • Experience with Synopsys and/or Cadence digital design tools/flows
  • Knowledge of design for test (DFT)
  • Familiarity with UVM based design verification
  • Silicon bring-up and debug experience
  • Small-geometry CMOS (≤28nm) design

Preferred Experience:

  • Scripting with Python or other equivalent programming languages.
  • Development/support for PCIe or Ethernet Switch products.